1. Field of the Invention
The present invention relates to a semiconductor memory device such as a RAM and the like capable of reading and writing data.
2. Prior Art
Up to now, after a semiconductor memory device has been manufactured the semiconductor memory device is evaluated in function using a memory tester, and thereby it is judged whether the semiconductor memory device is acceptable or defective. Such a memory tester has a probe card and a tester main body. The probe card has conductive needles arranged correspondingly to the arrangement of terminals of a semiconductor memory device in order to be connected with the respective terminals of the semiconductor memory device. The tester main body comprises an algorithmic pattern generator (ALPG) and a comparator. The ALPG generates in order an address signal corresponding to a memory cell to have data read from or written to it and expected value data to be expected when reading data written into a memory cell corresponding to each address, and the like. The comparator compares data read from a memory cell corresponding to each address with expected value data corresponding to the relevant address.
A test using a memory tester is performed in the following manner. First, the needles of a probe card are brought into contact with the terminals of a semiconductor memory device. Next, a tester main body sends address signals and test data to the semiconductor memory device through the probe card from an ALPG and thereby writes data into memory cells corresponding to the respective addresses. After this, the tester main body reads the data written into the respective memory cells. And the comparator judges whether or not the data obtained in a read operation coincide with the written data, namely, expected value data. When they coincide with each other, the said semiconductor memory device is determined to be acceptable, and when they do not coincide, the said semiconductor memory device is determined to be defective.
By the way, the larger the memory capacity of a semiconductor memory device is made, the more expensive a memory tester to be used in function test of the semiconductor memory device is made. The reason is that an ALPG of the memory tester is made larger in capacity and further its test speed needs to be made higher. And it is because since the number of needles of the probe card is increased, its manufacturing cost is made higher. Due to this, it is desired to realize a semiconductor memory device capable of performing a memory function test without using an expensive memory tester.
The present invention has been performed on the basis of the above circumstances, and an object of the invention is to provide a semiconductor memory device capable of performing a memory function test without using an expensive memory tester.
In order to attain the above object, the present invention is characterized by a semiconductor memory device capable of reading and writing data, comprising a counter circuit for generating a signal having a specific bit width each time a clock signal is inputted, a first selector circuit for selecting and sending one of an external address signal inputted from the outside and an internal address signal obtained by utilizing a signal from said counter circuit to a decoder, a second selector circuit for selecting and taking one of external data inputted from the outside and internal data obtained by utilizing a signal from said counter circuit as data to be written to a memory area corresponding to a specific address, a control circuit which makes said first selector circuit select said internal address signal and makes said second selector circuit select said internal data in case that a signal for performing a self-diagnostic test in relation to a memory function is inputted, and thereby writes said internal data sent from said second selector circuit into a memory area corresponding to an address specified by said internal address signal each time said internal address signal is sent from said first selector circuit and, after it has written data into every memory area, reads data from a memory area corresponding to an address specified by said internal address signal each time said internal address signal is sent from said first selector circuit, and a comparator circuit which compares data read from each memory area at the time of a data reading operation by said control circuit with expected value data obtained by utilizing a signal issued from said counter circuit at the time of the said read operation, and outputs, the result of comparison.
And in order to attain the above object, the present invention is characterized by a semiconductor memory device capable of reading and writing data, comprising; a counter circuit for generating a signal having a specific bit width each time a clock signal is inputted, a first selector circuit for selecting and sending one of an external address signal inputted from the outside and an internal address signal obtained by utilizing a signal from said counter circuit to a decoder, a second selector circuit for selecting and taking one of external data inputted from the outside and internal data obtained by utilizing a signal from said counter circuit as data to be written to a memory area corresponding to a specific address, a control circuit which makes said first selector circuit select said internal address signal and makes said second selector circuit select said internal data in case that a signal for performing a self-diagnostic test in relation to a memory function is inputted, and thereby writes said internal data sent from said second selector circuit into a memory area corresponding to an address specified by said internal address signal each time said internal address signal is sent from said first selector circuit and, after it has written data into every memory area, reads data from a memory area corresponding to an address specified by said internal address signal each time said internal address signal is sent from said first selector circuit, a first output terminal for outputting data read from each memory area, and a second output terminal for outputting expected value data obtained by utilizing a signal issued from said counter circuit at the time of a data reading operation by said control circuit.